(1) Field of the Invention
The present invention relates to computer systems. More specifically, the present invention relates to method and apparatus for the exchange of data at a high rate of speed among components within a computer system.
(2) Art Background
Data buses are used commonly throughout the computer industry. A bus is a set of hardware lines or wires used for data transfer among the components of a computer system. A bus is essentially a shared highway that connects different parts of the system, for example the microprocessor, disk drive controller, memory and input/output (I/O) ports, and enables them to transfer information. Usually supervised by the microprocessor, the bus is commonly specialized for carrying different types of information. One group of wires (actually, traces on a printed circuit board), for example, carries data; another carries the addresses (locations) where specific information can be found; yet another carries control signals to ensure that the different parts of the system use their shared highway without conflict. A communication protocol, or set of rules or standards, for the bus enables the components of the computer to connect with one another and to exchange information with as little error as possible.
Buses are characterized by the number of bits they can transfer at a single time. A computer with an 8-bit data bus, for example, transfers 8 bits of data at a time, and one with a 16-bit data bus transfers 16 bits at a time.
Because the bus is integral to internal data transfer and yet computer users often need to add extra components to the system, most microcomputer buses allow for expansion through one or more expansion slots (connectors for add-on circuit boards). Such boards, when they are added, make an electrical connection to the bus and effectively become part of the system.
FIG. 1 illustrates a computer system which has components coupled with a bus. In the Figure, bus 20 couples processor 10 to devices 12, 14, 16 and 18. Devices 12, 14, 16 and 18 are representative of generic computer components which exchange data among themselves or with the processor. Examples of devices 12, 14, 16 and 18 include: input/output (I/O) devices, status and control registers, random access memory (RAM) and programmable read only memory (PROM).
Processor 10 and each of the devices 12, 14, 16, and 18 are connected in parallel to bus 20. Each of the devices 12, 14, 16, and 18 and processor 10 present a capacitive and inductive load to bus 20. Modern processors may run at speeds of approximately 50 megahertz. However, connecting several loads to data bus 20 in parallel creates too much capacitive loading to permit data to be transferred across bus 20 at the operating speed of a 50 megahertz processor 10.
Referring now to FIG. 2, a computer system with two buses coupled by a bi-directional register is illustrated. In the figure, bus 24 couples processor 10 and device 18 to bi-directional register 22. Bus 26 couples devices 12, 14 and 16 to bi-directional register 22. By introducing a bi-directional register 22, and two separate buses 24 and 26, the load on each bus is decreased, thereby permitting faster communication along each bus.
In the example of FIG. 1, bus 20 was presented with five loads (processor 10 and devices 12, 14, 16, and 18). In the configuration of FIG. 2, bus 24 is presented with three loads (processor 10, device 18 and bi-directional register 22) and bus 26 is presented with four loads (devices 12, 14, and 16 and bi-directional register 22). Thus, while the total number of loads in the system has increased, the load on any given bus has decreased thereby permitting each bus to operate at a higher speed. While only one bi-directional register 22 has been introduced for ease of understanding, bus 24 and bus 26 could each be further subdivided by introducing additional bi-directional registers 22 between the devices attached to them.
While the introduction of one or more bi-directional registers 22 increases the speed at which each individual data bus can operate, there is a complexity penalty and a latency penalty which much be paid. The complexity penalty has several parts. First, each bi-directional register 22 has a significant number of parts and therefore this method introduces a significant number of additional chips into the computer system. Each chip consumes area within the computer system which could otherwise be used for other purposes or eliminated to reduce the size of the computer system. Each chip also consumes power which must be provided and produces heat which may have to be dissipated. Furthermore, routing can become an issue because each bi-directional register 22 may have to be routed to different parts all over the board. Therefore, introduction of bi-directional registers 22 increases the complexity of the design of the computer system.
Furthermore, there is latency penalty because, while the load has been reduced, signals will probably have to travel through one or more bi-directional registers 22.